“Recent Trends and Advances in High Performance Fractional-N PLL Design” by Wanghua Wu, PhD, Senior Principal Engineer and Design Manager, Samsung Semiconductor Inc. USA. IEEE Distinguished Lecturer.
Date: April 29, 2023 (Saturday)
Time: 09:00 hrs till 10:00 hrs (UTC+8)
Google Meet: https://meet.google.com/sow-kvfy-izr
High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, fast locking, and low power operation. Both circuits design and digital calibration techniques will be presented in detail. In addition, recent advances in reference clock generation will also be discussed as it is crucial for high performance PLLs.
Wanghua Wu (M’07) received the B.Sc. degree (with honors) from Fudan University, Shanghai, China, in 2004, M.Sc. degree (cum laude) and Ph.D. degree from Delft University of Technology, The Netherlands in 2007 and 2013, respectively, all in electrical engineering. From 2013 to 2016, she was an RFIC Design Engineer in Marvell, developing high-performance frequency synthesizers for WLAN transceivers. Since 2016, she has been with Samsung Semiconductor Inc. USA. She is currently a Senior Principal Engineer and Design Manager, focusing on advanced cellular RFIC design. Her research interest is on CMOS frequency synthesis for wireless applications. She serves on the Technical Program Committee of IEEE International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), and Radio Frequency Integrated Circuits Symposium (RFIC). She serves as a Distinguished Lecturer for the IEEE Solid-State Circuits Society.